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XUP PYNQ-ZU

01_PYNQ-ZU
Overview

PYNQ- Python Productivity for Zynq

PYNQ is an open-source project from Xilinx® that makes it easier to use Xilinx platforms. Using the Python language and libraries, designers can exploit the benefits of programmable logic and microprocessors to build more capable and exciting electronic systems.

What is included?

  • The PYNQ-ZU board featuring the Zynq UltraScale+ XCZU5EG-1SFVC784 MPSoC.
  • 16GB Micro SD Card.
  • Power supply 12V 5A output. Model KPL-060F-VI.

Additional Required Items

  • Micro-USB cable

Zynq Ultrascale+ MPSoC Features

  • 64-bit Quadcore ARM Cortex-A53 Processors
  • Dualcore ARM Cortex-R5 Real-Time Processors
  • ARM Mali™-400MP Graphics Processor
  • H.265/264 Video Codec Unit
  • Separate 32 KB L1 caches for instruction and data
  • Two-stage (hypervisor and guest stages) memory management unit (MMU)
  • 1 MB L2 cache in CCI coherency domain.
  • Accelerator coherency port (ACP).
  • 128-bit AXI coherency extension (ACE) master interface to CCI
  • 256 KB On-Chip Memory
  • 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
  • 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO on-chip peripherals
  • 117K CLB LUTs
  • 5.1 Mb Block RAM
  • 18 Mb Ultra RAM
  • 1,248 DSP Slices
  • Four clock management tiles, each with phase-locked loop (PLL)
  • Internal clock speeds exceeding 450MHz
  • 2x 12 bit, 1 MSPS On-chip analog-to-digital converter (XADC)
Hardware

Key Features

Feature Description
FPGA
  • Zynq UltraScale+ XCZU5EG-1SFVC784 MPSoC
I/O Interfaces
  • Micro USB-JTAG Programming circuitry
  • USB 3.0 OTG PHY (supports host only)
  • Micro USB-UART bridge
  • USB Composite 3.0
  • 4x USB 3.0
  • HDMI 2.0 sink port (input)
  • HDMI 2.0 source port (output)
  • Mini Display Port
  • Audio Codec
  • XADC
  • Wifi + Bluetooth
Memory
  • 4GB DDR4 2400R (64 bits wide)
  • Micro SD slot
Switches and LEDs
  • 4 push-buttons
  • 4 slide switches
  • 4 LEDs
  • 2 RGB LEDs
Clocks
  • PL clock 125MHz
  • PL User clock 156.25 MHz
  • Display Port Clock 27 MHz
  • USB 3.0 Clock 26 MHz
  • PS Clock 33.333MHz
Expansion ports
  • 2 standard Pmod ports and 1 TPM Pmod
  • MIPI CSI
  • FMC LPC
  • 40-pin Raspberry Pi connector
  • 3x Grove
  • Dual SYZYGY Interfaces
Tools & IP

Vivado

Vivado® ML is the Xilinx software suite for HDL and system-level design. Vivado includes a HDL simulator, IP Integrator for system-level integration, and tools for synthesis, implementation, bitstream generation and programming of Xilinx platforms.

Vivado Standard edition is a device limited version of the full Vivado enterprise edition and is free-of-charge and does not require a separate license.Licenses for the Vivado Enterprise edition which includes support for all Xilinx devices are available to universities from theXUP donation program.

You can select the free Vivado standard edition or the full Enterprise edition when you run the installer.

Download the Vivado installer

Vitis

Vitis™ is the Xilinx design software for targeting Alveo acceleration cards. It also includes software development tools for Xilinx embedded devices including the Zynq families. Vitis includes Vitis HLS, a C-based High-Level-Synthesis design tool that can be used standalone or from within Vitis for creating hardware accelerated kernel. Vitis is free of charge and does not require a separate license.

Download the Vitis installer

ContactXUPif you have any questions about Xilinx software or to discuss your requirements.

Purchasing and more information

Purchase the PYNQ-ZU from our partner:TUL

Visit thePYNQ-ZU project page