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  6. Advanced Embedded System Design on Zynq using Vivado

Advanced Embedded System Design on Zynq using Vivado

Course Description This workshop provides professor the necessary skills to develop complex embedded systems using Vivado design suite; understand and utilize advanced development techniques of embedded systems design for architecting a complex system in the Zynq® System on a Chip (SoC).
Level Intermediate
Duration 2 Days
Who should attend? Professors who are familiar with embedded system design using Vivado and want to explore advanced design techniques using Xilinx SoC in Zynq.
Pre-requisites
  • Digital logic and FPGA design experience
  • Experience with Vivado software
  • Experience with Embedded System design
  • Have attended XUP Embedded System Design workshop or has an equivalent experience

Skills Gained

After completing this workshop, you will be able to:

  • Assemble an advanced embedded system
  • Explore various features of Zynq Soc for hardware-software co-design
  • Design and integrate peripherals using interrupts
  • Analyze system performance
  • Utilize hardware debugging technique
  • Design a bootable system ready for deployment in field

Course Overview

Day 1:

  • Review Embedded System Design in Zynq using Vivado
  • Lab 1: Create a SoC-Based System using Programmable Logic
    • Create a complete processor system with built-in processor and IP in programmable logic.
  • Advanced Zynq Architecture
  • System Debugging using Vivado Logic Analyzer and SDK
  • Lab 2: Debugging using Vivado Logic Analyzer cores
    • Insert various Vivado Logic Analyzer cores to debug/analyze system behavior.
  • Memory Interfacing
  • Lab 3: Extending Memory Space with Block RAM
    • Instantiate AXI BRAM controller and BRAM to extend address space and run application from it.

Day 2:

  • Interrupts
  • Low Latency High Bandwidth
  • Lab 4: Direct Memory Access using CDMA
    • Perform DMA operations between various memories using AXI CDMA controller in polling and interrupt modes.
  • Processor Configuration and Bootloader
  • Lab 5: Configuration and Booting
    • Create images to boot off the SD card and QSPI flash. Load previously generated hardware bitstreams and executables, and execute desired application.
  • Profiling and Performance Improvement
  • Lab 6: Profiling and Performance Tuning
    • Profile an application performing a function both in software and hardware.

Quick Links

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Common to PYNQ-Z1 and PYNQ-Z2

PYNQ-Z1

PYNQ-Z2

Common to ZedBoard and ZYBO

ZedBoard

ZYBO