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描述
The Rambus DMA Back-End Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems. The core works with the Xilinx FPGA hard cores. It can be configured with multiple DMA Engines which each have their own interface. It supports Packet/Block and Addressed/Non-addressed transfers. Host-based and local descriptors are supported. The core supports legacy, MSI and MSI-X interrupts. Using the core eliminates the need for the user to implement their own DMA design, significantly reducing development time and risk. Companion Windows and Linux DMA drivers are available. The DMA Back-End Driver works hand-in-hand with the DMA Back-End core to implement host-based, scatter-gather DMA operation. Note: Utilization numbers provided in the 'IP Implementation and Quality Metrics' tab is for a x1 lane DMA Back-End Core implementation
主要特性與優勢
- Utilization numbers provided in the IP Implementation and Quality Metrics are for a x1 lane PCIe implementation
- Provided with a PCI Express Testbench
- Works with Xilinx PCI Express hard cores and Northwest Logic soft PCI Express cores
- Fully hardware validated
- Supports host-based and local descriptors
- Supports Packet/Block and Addressed/Non-addressed transfers
- Provides maximum DMA throughput in both System->Card and Card->System directions
- Also available with AXI user interface
- Companion Windows and Linux DMA Drivers available
- Can be configured with multiple independent DMA Engines
- Provides high performance, scatter-gather DMA operation
