Vivado 2012.1/ISE® 14.1 IP Updates (May 8, 2012)

Public access support for the Zynq™-7000, device families has been added to a selection of cores in this release.

For a comprehensive listing of IP cores supporting these new device families, see the table below.

The release also includes updates to these other popular IP cores:

• Building Block IP
  • Architecture Wizards*
  • Block Memory Generator*
  • FIFO Generator*
  • Memory Interface Generator (MIG)*
• Connectivity
  • PCI Express
• DSP Building Block IP
  • Floating Point Operator*
  • FFT*
• FPGA Features and Debug
  • 7 Series FPGAs Transceivers Wizard

The release also includes the following new LogiCORE IP:

• Audio, Video and Image Processing
  • Asynchronous Sample Rate Converter (ASRC)*
  • AXI4-Stream to Video Output*
  • Video Input to AXI4-Stream*
• Bus Interface and IO
  • DisplayPort with Audio (SPDIF)
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)*
• Communications and Networking
  • 10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation for Backplanes (10GBASE-KR)
  • SMPTE2022-5/6 Video over IP
• Embedded Processing
  • I/O Module*
  • AXI System Cache*
• FPGA Features and Debug
  • ChipScope Pro IBERT for 7 Series GTH*
  • ChipScope Pro IBERT for 7 Series GTX*
• Interconnect Infrastructure
  • AXI Performance Monitor**
  • AXI4 Stream Interconnect*
  • AXI Virtual FIFO Controller*

• Audio, Video & Image Processing
• Basic Logic
• Communications & Networking
• Digital Signal Processing
• Embedded Processing
• FPGA Features & Debug
• Interconnect Infrastructure
• Math Functions
• Memories & Storage Elements
• Standard Bus Interfaces