IMPORTANT NOTICE
For access to XAUI/RXAUI support after 2019.1, please contactMissing Link Electronics
Product Description
No charge paramaterizable core which utilizes the serial I/O transceivers available in the Kintex® UltraScale™, Virtex® UltraScale, Virtex-7, Kintex-7, Artix®-7, Zynq®-7000, Virtex-6, Virtex-5, Virtex-4 FX, Virtex-II Pro and Spartan®-6 to support the XAUI function.
The Xilinx 10 Gigabit Attachment Unit Interface (XAUI) LogiCORE™ IP provides a 4-lane high speed serial interface, providing up to 10 Gigabits per second (Gbps) total throughput. Operating at an internal clock speed of 156.25 MHz, the core includes the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 ofIEEE 802.3-2012. In addition, the core supports an optional serial MDIO management interface for accessing theIEEE 802.3-2012clause 45 management registers. The MDIO interface may be omitted to save logic, in which case a simplified management interface is provided via bit vectors.
The design conforms to theIEEE 802.3ae-2012standard and includes the following functionality:
- 8B10B encode/decode with error detection
- Comma detection
- RX elastic buffer/channel bonding
- A state-of-the-art PMA (SERDES)
- Idle generation on transmit
- Synchronization state machine on each receive lane
- Deskew state machine on receive (Channel Bonding)
- Full set of management registers (perIEEE 802.3aespecifications)
The XAUI core is ideally suited to provide high-performance interconnect technologies for communications equipment and facilitate easy interfacing with 10 Gbps transceivers supporting this standard (XENPAK compliant devices, for example).
Key Features and Benefits
- Single chip solution for XAUI applications
- Supports 20G double-rate XAUI (Double XAUI) in 7 series and Virtex-6 devices using four transceivers at 6.25 Gb/s
- Designed toIEEE 802.3-2008specification
- Allows direct interfacing between 7 series, Virtex-6, Virtex-5, Virtex-4 FX, Virtex-II Pro, or Spartan-6 FPGAs and industry standard ASSP PHY devices
- Supports 32 bit DDR or 64 bit SDR backend interface
- Uses Digital Clock Management or mixed mode Clock Managers to implement optional XGMII interface clocking
- Leverages DDR I/O primitives for the optional XGMII interface
- Uses 7 series, Virtex-6, Virtex-5, Virtex-4, and Spartan-6 transceivers running 4 lanes at 3.125Gbps for the XAUI interface
- Optional802.3-2008clause 48 State Machines
- Implements DTE XGXS, PHY XGXS and 10G BASE-X PCS in a single netlist
- Supports 10-Gigabit Fibre Channel (10-GFC) XAUI data rates and traffic