Production support for AXI IP has been added in this release for 12.4 AXI-based designs.
This release of Xilinx CORE Generator includes two IP cores which have been updated with AXI4 support.
New Cores Versions | Additional License Required | Datasheet (PDF) | AXI4 | Spartan-3E | Extended Spartan-3A Families | Spartan-6 | Virtex-4 | Virtex-5 | Virtex-6 | |
Audio, Video & Image Processing | ||||||||||
Color Filter Array(v3.0) | ✓ | DS722 | ✓ | ✓ | ✓ | ✓ | ||||
Image Edge Enhancement(v2.0) | ✓ | DS753 | ✓ | ✓ | ✓ | ✓ | ||||
Image noise Reduction (v2.0) | ✓ | DS751 | ✓ | ✓ | ✓ | ✓ | ||||
Communications & Networking | ||||||||||
Aurora | Additional License Required | Datasheet (PDF) | AXI4 | Spartan-3E | Extended Spartan-3A Families | Spartan-6 | Virtex-4 | Virtex-5 | Virtex-6 | |
Aurora 64B/66B(v5.1) | DS815(AXI) |
AXI4-Stream | ✓ | ✓ | ||||||
Error Correction | ||||||||||
Soft Error Mitigation (SEM)(v1.2) | DS796 | ✓ | ||||||||
Telecommunications | ||||||||||
SPI-3 Link Layer Interface, Multi-channel (v7.3) | ✓ | DS504 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ||
SPI-4.2(v10.3) | ✓ | DS209 | ✓ | ✓ | ✓ | |||||
Wireless | ||||||||||
3GPP LTE MIMO Decoder (v2.0) | ✓ | XPM040 | AXI4-Stream | ✓ | ✓ | ✓ | ||||
Digital Signal Processing | ||||||||||
FIR Compiler(v6.1) | DS795(AXI) |
AXI4-Stream | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ||
FPGA Features & Design | ||||||||||
Clock Wizard(v1.8) | DS709 | ✓ | ✓ | |||||||
SelectIO Interface Wizard(v1.5) | DS746 | ✓ | ✓ | |||||||
Spartan®-6 FPGA GTP Transceiver Wizard(v1.8) | DS713 | ✓ | ||||||||
System Monitor Wizard(v2.1) | DS608 | ✓ | ✓ | ✓ | ||||||
Virtex®-6 FPGA GTH Transceiver Wizard(v1.6) | DS738 | ✓ | ||||||||
Virtex-6 FPGA GTX Transceiver Wizard(v1.8) | DS708 | ✓ | ||||||||
Memories & Storage Elements | ||||||||||
Memory Interface Generator(MIG) (v3.61) | MIG | AXI4 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ||
Standard Bus Interfaces | ||||||||||
PCI Express® | Additional License Required | Datasheet (PDF) | AXI4 | Spartan-3E | Extended Spartan-3A Families | Spartan-6 | Virtex-4 | Virtex-5 | Virtex-6 | |
Spartan-6 FPGA Integrated Endpoint Block for PCI Express(PCIe) (v2.2) | ✓ | DS801(AXI) |
AXI4-Stream | ✓ | ||||||
Virtex-6 Integrated Block for PCI Express(PCIe) (v2.2) | ✓ | DS800(AXI) |
AXI4-Stream | ✓ |
*Included with ISE at no additional charge
Comments, Questions, or Problems? Please enter aWebCase(Internet Explorer is required)