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Zynq UltraScale+ RFSoC Design Overview

Design Resources

Design Resources

User Guides and Tutorials Design Files Date
UG1075 -Zynq UltraScale+ Device Packaging and Pinouts Product Specification 07/01/2021
UG583 -UltraScale Architecture PCB Design User Guide 06/03/2021
UG440 -Xilinx Power Estimator User Guide 12/20/2018
UG578 -UltraScale Architecture GTY Transceivers User Guide 09/20/2017
PG182 -UltraScale FPGAs Transceivers Wizard v1.7 Product Guide for Vivado Design Suite 12/04/2020
RF Analyzer Tutorial
White Papers Design Files Date
WP517 -Extending the Thermal Solution by Utilizing Excursion Temperatures 10/23/2019
WP489 -An Adaptable Direct RF-Sampling Solution 02/20/2019
WP498 -Integrated SD-FEC in Zynq UltraScale+ RFSoCs for Higher Throughput and Power Efficiency 05/29/2018
WP509 -Understanding Key Parameters for RF-Sampling Data Converters 02/20/2019
Reports Design Files Date
Zynq UltraScale+ Characterization Reports
Design Advisories Design Files Date
AR73277 -Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: 2018.x-2019.1 XilSKey resets the PS System Monitor configuration 02/07/2020
AR73282 -Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: 2018.x/2019.x XilSKey does NOT exit BBRAM Programming Mode 02/07/2020
AR72994 -Design Advisory for Zynq UltraScale+ MPSoC/RFSoC - 2019.1 XilSKey: PPK Hash buffer overflow 11/08/2019
AR72768 -Design Advisory for Zynq UltraScale+ MPSoC/RFSoC - 2019.1 FSBL: Image Header Table (IHT) Buffer Overflow 11/08/2019
AR72572 -Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: 2019.1 XilSKeyPUF Registration is incorrect 08/08/2019
AR72588 -Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: Encrypt Only Boot Mode - Unauthenticated Boot and Partition Headers 08/08/2019
AR72499 -Design Advisory for Zynq UltraScale+ MPSoC/RFSoC - PS LPDDR4 DRAM devices require WDQS Control to be enabled 04/23/2021
AR71952 -Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: A glitch might be observed on the PMU GPO1[2] (MIO34) following assertion of PS_POR_B 04/26/2019
AR72003 -Design Advisory for Zynq UltraScale+ MPSoC/RFSoC - MIO26 cannot be used for GEM TSU_REF_CLK 04/05/2019
AR71953 -Design Advisory for Zynq UltraScale+ MPSoC/RFSoC Processing System - MIO Slew and Input Type register settings incorrect 04/05/2019
AR71901 -Design Advisory ZCU104 and ZCU111 - Infineon IRPS5401 has a drive signal of 5V for an external power stage 01/17/2019
AR70394 -Are Xilinx Zynq-7000 and Zynq UltraScale+ MPSoC & RFSoC devices affected by the Meltdown and Spectre vulnerabilities? 05/15/2018
Design Hubs Design Files Date
DH0070 -Zynq UltraScale+ MPSoC Design Overview 06/16/2021
Application Notes Design Files Date
XAPP1331 -Aurora 8B10B for GTY UltraScale+, Zynq UltraScale+ MPSoC and RFSoC Design Files 06/06/2018

Support Resources

Support Resources

Errata Date
EN291 -Zynq UltraScale+ RFSoC Production Errata 03/29/2021
Solution Centers Date
AR55831 -Software Developer Solution Center 02/15/2016
Xilinx Forums Date
Support Community