Memory Interfaces Design Hub - UltraScale DDR3/DDR4 Memory
This page coversMemory InterfacinginUltraScale Devicesusing theMemory Interface Generator (MIG)in theVivado Design Suite
Additional Learning Materials
| User Guides | Date |
|---|---|
 UG583 -UltraScale Architecture PCB Design Guide |
06/03/2021 |
| UG571 -UltraScale Architecture SelectIO Resources User Guide |
08/28/2019 |
| UG572 -UltraScale Architecture Clocking Resources User Guide |
08/28/2020 |
| Vivado Design Hubs | Date |
 DH0007 -I/O and Clock Planning |
06/16/2021 |
| DH0003 -Designing with IP |
06/16/2021 |
| DH0009 -Using IP Integrator |
06/16/2021 |
| Memory Interface Design Tips | Date |
| PG150 -Migrating Memory IP Using Vivado |
08/11/2021 |
| UG583 -PCB Trace Derating |
06/03/2021 |
| PG150 -Using the Memory IP Traffic Generator |
08/11/2021 |
| Targeted Reference Designs | Date |
| DH0043 -Kintex UltraScale FPGA KCU105 Evaluation Kit |
06/16/2021 |
Support Resources
Please visit theXilinx Service Portalto open or review a service request.
| Solution Centers | Date |
|---|---|
 AR34243 -Xilinx Memory IP Solution Center |
04/26/2016 |
| Design Advisories | Date |
| AR33566 -Design Advisories for Memory Interfaces |
08/25/2020 |
| Known Issues | Date |
| AR73052 -UltraScale/UltraScale+ DDR3/DDR4 IP - [Mig 66-119] Phy Core Regeneration & Stitching Failed |
06/11/2020 |
| AR69035 -DDR4 UltraScale and UltraScale+ IP Release Notes and Known Issues |
03/31/2021 |
| AR69036 -DDR3 UltraScale and UltraScale+ IP Release Notes and Known Issues |
03/31/2021 |
| Debug Resources | Date |
| PG150 -Using the Memory Interface Debug GUI and XSDB for Calibration Failures |
08/11/2021 |
| PG150 -Debugging Data Errors |
08/11/2021 |
 XTP359 -Memory Interface UltraScale Design Checklist |
|
| AR62181 -Hardware Debug Guide - Debugging Memory Interface Issues |
|
| Forums | Date |
| Support Community |
