Virtex-7 FPGA Kits

The Virtex-7 FPGA VC707 Evaluation Kit is a full-featured, highly-flexible, high-speed serial base platform using the Virtex-7 XC7VX485T-2FFG1761C and includes basic components of hardware, design tools, IP, and pre-verified reference designs for system designs that demand high-performance, serial connectivity and advanced memory interfacing. The included pre-verified reference designs and industry-standard FPGA Mezzanine Connectors (FMC) allow scaling and customization with daughter cards.

The Virtex-7 FPGA VC7222 Characterization Kit provides the hardware environment for characterizing and evaluating the GTH and GTZ transceivers available on the Virtex-7 XC7VH580T-2HCG1155CES9885 FPGA.

The Virtex-7 FPGA VC7203 Characterization Kit provides the hardware environment for characterizing and evaluating 28 GTX (12.5Gbps) transceivers of the on-board Virtex-7 V485T FPGA. The VC7203 allows evaluation of the Integrated Bit Error Ratio Test (IBERT) demonstration using either the Vivado or ISE design suites. Each GTX Quad and its associated reference clock are routed from the FPGA to a connector pad which is designed to interface with a Samtec BullsEye connector. A cable enabled with a BullsEye connector and 10 standard SMAs allows users to connect to a broad range of evaluation platforms, from backplanes and optical evaluation boards to high speed test equipment. Each BullsEye connector handles a full GTX Quad, four transmit/receive pairs as well as the two independent reference clocks, enabling the highest level of flexibility in testing custom applications.

The Virtex-7 FPGA VC709 Connectivity Kit is a 40Gb/s platform for high-bandwidth and high-performance applications containing all the necessary hardware, software and IP to power quickly through your evaluation and development of connectivity systems. This includes a 40Gb/s targeted reference design featuring PCI Express Gen 3, a DMA IP core from Northwest Logic, 10GBase-R, AXI, and a Virtual FIFO memory controller interfacing to an external DDR3 memory. To control and monitor this design, the kit includes a connectivity GUI built on Fedora Live OS which includes all the software drivers. Additionally, this kit contains two fiber optic cables and four transceiver modules leveraged by this design.

The Getting Started Guide and the Targeted Reference Design are based on the 2013.2 version of the Vivado Design Suite. There are no plans to update the code or documents.

Product Page	Design Files	Date
Virtex-7 FPGA VC709 Connectivity Kit - Product Page
User Guides	Design Files	Date
UG966 -Virtex-7 XT VC709 Connectivity Kit Getting Started Guide (Vivado Design Suite 2014.3)	rdf0285-vc709-connectivity-trd-2014-3.zip	12/03/2014
UG887 -VC709 Evaluation Board for the Virtex-7 FPGA User Guide		03/11/2019

The Virtex-7 FPGA VC7215 Characterization Kit provides the hardware environment for characterizing and evaluating 80 GTH (13.1Gbps) transceivers of the on-board Virtex-7 V690T FPGA. The VC7215 allows evaluation of the Integrated Bit Error Ratio Test (IBERT) demonstration using the Vivado design suite. Each GTH Quad and its associated reference clock are routed from the FPGA to a connector pad which is designed to interface with a Samtec BullsEye connector. A cable enabled with a BullsEye connector and 10 standard SMAs allows users to connect to a broad range of evaluation platforms, from backplanes and optical evaluation boards to high speed test equipment. Each BullsEye connector handles a full GTH Quad, four transmit/receive pairs as well as the two independent reference clocks, enabling the highest level of flexibility in testing custom applications.