Kintex-7 FPGA Kits

The Kintex-7 FPGA KC705 Evaluation Kit includes all the basic components of hardware, design tools, IP, and pre-verified reference designs including a targeted design enabling high-performance serial connectivity and advanced memory interfacing. The included pre-verified reference designs and industry-standard FPGA Mezzanine Connectors (FMC) allow scaling and customization with daughter cards.

TheKintex-7 Embedded Kitincludes the components of theKintex-7 KC705 Base Evaluation Kitplus all additional soft content that embedded designers need to quickly design their high-performance embedded systems. This includes the embedded targeted reference design and relevant tools such as Vivado Design Suite.

Refer to theKC705 Evaluation Kit Design Hubto access the docs and designs for the KC705 evaluation kit.

The Getting Started Guide and the Targeted Reference Design were last updated for 2013.2. There are no plans to update the code or document using future Vivado tool releases.

Product Page	Date
Kintex-7 FPGA Embedded Kit - Product Page
User Guides	Date
UG913 -Getting Started with the Kintex-7 FPGA KC705 Embedded Kit User Guide (Vivado Design Suite 2013.2)	03/07/2014
Data Sheets	Date
DS669 -AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet	04/23/2013

Additional designs are available from theKC705 Evaluation Kit Design Hub.

Kintex-7 Embedded Kit - Reference Designs	Design Files	Date
UG985 -Kintex-7 FPGA Embedded Targeted Reference Design User Guide (Vivado Design Suite 2013.2)	Kintex-7 FPGA Embedded Kit Targeted Reference Design (ver 2013.2)	08/29/2013

Additional board files are available from the KC705 Evaluation Kit Design Hub.

KC705 Schematics and Allegro Board Files	Design Files	Date
XTP132 -KC705 Schematics PDF (Rev 1.1)	kc705_Schematic_Source_rdf0146_rev1_1.zip kc705_BOM_rdf0149_rev1_0.zip kc705-ucf-xdc-rdf0150-rev1-0.zip
XTP133 -KC705 Allegro Board PDF (ZIP) (Rev 1.0)	kc705_Allegro_Board_Source_rdf0147_rev1_0.zip kc705_Gerber_Files_rdf0148_rev1_0.zip
Additional Resources	Design Files	Date
XTP280 -Kintex-7 Embedded CE Declaration of Conformity		10/01/2013

References listed below are specific to Kintex-7 Connectivity Kit. Please refer to theKC705 Evaluation Kit Design Hubfor additional resources.

Solution Center and Known Issues	Date
AR43745 -Xilinx Boards and Kits Solution Center	03/31/2017
AR52970 -Kintex-7 FPGA Embedded Kit - Known Issues and Release Notes Master Answer Record	01/10/2014
AR56174 -Kintex-7 FPGA Embedded Targeted Reference Design - Release Notes and Known Issues Master Answer Record

The Kintex-7 FPGA Connectivity Kit is a 20Gb/s platform for high-bandwidth and high-performance applications containing all the necessary hardware, software and IP to power quickly through your evaluation and development of connectivity systems. This includes a 20Gb/s targeted reference design featuring PCI Express, a DMA IP core from Northwest Logic, 10GBase-R, AXI, and a Virtual FIFO memory controller interfacing to an external DDR3 memory. To control and monitor this design, the board includes a connectivity GUI built on Fedora Live OS which includes all the software drivers. Additionally, this board contains the relevant SFP+ FMC daughter card, cable and transceiver modules needed to utilize this design.

This kit includes theKC705 Evaluation Boardfeaturing the XC7K325T-2FFG900C FPGA.

Additional designs are available from theKC705 Evaluation Kit Design Hub.

Kintex-7 Connectivity Kit - Reference Designs	Design Files	Date
UG927 -Kintex-7 FPGA Connectivity Targeted Reference Design User Guide (Vivado Design Suite 2014.3)	rdf0282-k7-connectivity-trd-2014-3.zip	12/18/2014
Application Notes	Design Files	Date
XAPP1179 -Using Tandem Configuration for PCIe in the Kintex-7 Connectivity TRD	xapp1179-tandem-config-pcie.zip	10/25/2013

Additional board files are available from the KC705 Evaluation Kit Design Hub.

KC705 Schematics and Allegro Board Files	Design Files	Date
XTP132 -KC705 Schematics PDF (Rev 1.1)	kc705_Schematic_Source_rdf0146_rev1_1.zip kc705_BOM_rdf0149_rev1_0.zip kc705-ucf-xdc-rdf0150-rev1-0.zip
XTP133 -KC705 Allegro Board PDF (ZIP) (Rev 1.0)	kc705_Allegro_Board_Source_rdf0147_rev1_0.zip kc705_Gerber_Files_rdf0148_rev1_0.zip
Additional Resources	Design Files	Date
XTP279 -Kintex-7 Connectivity CE Declaration of Conformity		10/01/2013

References listed below are specific to Kintex-7 Connectivity Kit. Please refer to theKC705 Evaluation Kit Design Hubfor additional resources.

Solution Center and Known Issues	Date
AR43745 -Xilinx Boards and Kits Solution Center	03/31/2017
AR50555 -Kintex-7 FPGA Connectivity Kit and Targeted Reference Design - Release Notes and Known Issues Master Answer Record	05/13/2013

The Kintex-7 FPGA KC724 Characterization Kit provides the hardware environment for characterizing and evaluating 16 GTX (12.5Gbps) transceivers of the on-board Kintex-7 K325T FPGA. The KC724 allows evaluation of the Integrated Bit Error Ratio Test (IBERT) demonstration using either the Vivado or ISE design suites. Each GTX Quad and its associated reference clock are routed from the FPGA to a connector pad which is designed to interface with a Samtec BullsEye connector. A cable enabled with a BullsEye connector and 10 standard SMAs allows users to connect to a broad range of evaluation platforms, from backplanes and optical evaluation boards to high speed test equipment. Each BullsEye connector handles a full GTX Quad, four transmit/receive pairs as well as the two independent reference clocks, enabling the highest level of flexibility in testing custom applications.